 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| W581XX Design Guide ADPCM VOICE SYNTHESIZER (Enhanced PowerSpeechTM) TM INTRODUCTION The W581XX family is an enhanced version of the W528X PowerSpeechTM synthesizer series. The W581XX family features a ADPCM synthesizer and an 8-bit D/A converter to generate various kinds of voice effects. It also provides Load and Jump commands, eight general and three specific purpose registers, and all other necessary control and timing logic circuit to implement more advanced applications. The W58100 is an emulation chip used for the purpose of demonstrating the W581XX series enhanced PowerSpeechTM products. The W581XX family includes the W58101, W58102, W58103, W58104, W58105, W58106, W58110, W58115, and the W58120. The ROM size of each of these products is shown below: BODY ROM Size W58101 80K W58102 160K W58103 240K W58104 320K W58105 512K W58106 768K W58110 1M W58115 1.5M W58120 2M FEATURES * * * * * * * Wide operating voltage range: 2.4 to 5.5 volts 4-bit ADPCM synthesis Four direct trigger inputs Two trigger input, long and short, debounce times Up to two LED and five STOP outputs Easily software extendable to 24 matrix trigger inputs Flexible functions programmable through the following: - LD (load), JP (jump) commands - Eight general purpose registers: R0~R7 - Three specific registers: EN, STOP, and MODE - Conditional instructions - Speech equations - END instruction - Output frequency and LED flash type setting * * * * * Fading effect (patent pending), and eight levels of SPK volume control can be set easily by section control Programmable power-on initialization (POI) (can be interrupted by trigger inputs) Every LED pin can simultaneously drive a maximum of three LEDs LED can be set as a volume control mode output LED flash frequency: 3 Hz Version E Release Date: April 1999 - 1- W581xx Design Guide AUD output current: 5 mA * POI delay time of 160 mS ensures stable voltage during chip power on * Can be programmed for the following functions: - Interrupt or non-interrupt for each trigger pin; rising or falling edge (this feature determines retriggerable, non-retriggerable, overwrite, and non-overwrite features of each trigger pin) - Four playing modes: One Shot (OS) Level Hold (LH) Single-cycle level hold (S_LH) Complete-cycle level hold (C_LH) - Stop output signal setting - Serial, direct, or random trigger mode setting * Four frequency options (4/4.8/6/8 KHz) and LED On/Off control can be set independently in each speech equation GO instruction * Independent control of LED 1 and LED 2 * Total of 256 voice group entries available for programming * Provides the following mask options: - LED flash type: synchronous/alternate - LED 1 section-controlled: Yes/No - LED 2 section-controlled/STPC-controlled - LED volume-controlled: No/Yes - FTEST/STPD (Note: The FTEST function is not provided on the W58100, only on W581XX.) - STPE/BUSY - NORMAL/CPU * Provides the following program declarations: - FREQ0, FREQ1, FREQ2, FREQ3: Frequency variable - LED0, LED1: LED on or off - VOL0~VOL7: Fading effect (patent pending) * - 2- W581xx Design Guide BLOCK DIAGRAM (W58100) OSC TIMING GENERATOR DATA TG1 TG2 TG3 TG4 LED 1 /DISOTP CONTROLLER STPA STPB LED2/STPC STPD STPE/BUSY /RESET EXTERNAL INTERFACE CIRCUIT RDP WRP SHIFT REGISTER ADPCM SYNTHESIZER D/A CONVERTER VDD VSS SPK PIN CONFIGURATION (W58100) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 WRP DATA RDP STPE/BUSY STPD(/FTEST) LED2/STPC /RESET /DISOTP OSC V DD TG1 TG2 TG3 TG4 LED1 STPB STPA NC SPK VSS * FTEST: not provided on W58100, but provided on W581xx - 3- W581xx Design Guide PIN DESCRIPTION (W58100) NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NAME TG1 TG2 TG3 TG4 LED1 STPB STPA NC SPK VSS VDD OSC /DISOTP /RESET LED2/STPC STPD(/FTEST) STPE/BUSY *RDP *DATA *WRP I/O I I I I O O O O O I I I O O O O I/O O Trigger Input 1 Trigger Input 2 Trigger Input 3 Trigger Input 4 LED 1 Stop Signal B Stop signal A No connected Current output for speaker Negative power supply Positive power supply Oscillation frequency control, connect Rosc to VDD Disable all of the serial interface pins (low active) Reset pin (low active) LED2 or Stop C output Stop D output (FTEST not provided on W58100) Stop E or Busy signal output Read pulse clock output for serial interface Bidirectional Data Pin for the serial interface Write pulse clock output for serial interface FUNCTION *: The RDP, WRP, and DATA pins are only provided on W58100. 1. TG1~TG4 These pins are pulled high internally by an equivalent resistance of around 1M ohm. After being activated these direct trigger inputs start executing the corresponding voice groups, which are located at 0/1/2/3 for falling edge triggers and at 4/5/6/7 for rising edge triggers. The priority is set as: TG1F > TG1R > TG2F > TG2R > TG3F > TG3R > TG4F > TG4R. When more than one trigger is activated, only the one with the highest priority is serviced; all other trigger pins are suppressed. 2. LED1, LED2 These pins are open-drain outputs to sink current through the LEDs. 3. STPA~STPE These are inverter-type stop output signals that can be used to drive external peripherals such as transistors, motors, or lamps. They are also useful in keypad scan applications with up to 24 keys. - 4- W581xx Design Guide In keypad matrix applications, TG1~TG4 function as the trigger inputs to initiate the software scan routine. These inputs determine which key has been pressed by determining which row (TG1 ~ TG4) and which column (Vss, STPA ~ STPE) has been connected. The 24 key matrix does not require additional components and is shown below: TG1 TG2 TG3 TG4 LED1 STPB STPA NC SPK VSS 1 2 20 19 WRP DATA RDP STPE/BUSY STPD/FTEST LED2/STPC /RESET /DISOTP OSC V DD W58100 3 4 5 6 7 8 9 10 18 17 16 15 14 13 12 11 4. STPE/BUSY This pin is configured as STPE or BUSY depending upon the program declaration of this pin. If this pin is not declared as either STPE or BUSY then it will default to STPE in NORMAL mode and as BUSY in CPU mode. The BUSY signal goes high whenever a successful interrupt occurs, whether the interrupt comes from POI, the micro-controller (CPU), or a trigger input. When an interrupt occurs, the BUSY signal goes high and stays high until the end of the operation. i.e. after encountering an "END" instruction the BUSY signal will be low. 5. STPD/FTEST This pin is configured as a STPD output or as a frequency output test pin, FTEST, depending on the program declaration of this pin. After being declared as an FTEST pin at the beginning of the program, this pin will generate a constant frequency output during playback. A counter can then be used to test this constant frequency in order to check whether the frequency deviation of this code is normal or abnormal. The constant frequency will be kept at 6K Hz, under the condition of the typical master frequency - for example, 3M Hz. 6. OSC A ring oscillator is used to generate the master frequency of about 3 MHz. This pin is connected with an Rosc resistor to VDD providing a bias current for the ring oscillator. - 5- W581xx Design Guide 7. WRP, RDP, and DATA These three pins are dedicated to the W58100 emulation chip and are used to communicate with external serial memory devices such as flash EPROMs. Using these three pins together with an W58100 chip allows for 100% emulation of code to be used in mass produced chips. 8. /DISOTP This pin is used to disable the three serial interface pins (WRP, RDP, and DATA) on the W58100 emulation chip. This allows the programming of a flash EPROM without disconnecting the interface pins in advance. This pin can be grounded to program the flash EPROM which is bonded on the COB and W58100. This concept is shown in the following diagram: WRITER PCB W58100 TG1 OSC SPK VDD VSS WRP DATA RDP /DISOTP 1 2 3 4 VPP MCLK Vss W55412A PGM VDD 8 7 6 5 1 2 3 4 5 6 7 8 1 2 3 4 8 7 6 5 1 8 RDP DATA WRP textool ground COB After programming, the /DISOTP pin must be floated in order to enable the WRP, DATA and RDP pins on the W58100. The sound effect of the flash EPROM can then be heard. 9. /RESET This is an active-low reset input with an internal pull-high resistance of 500K ohm. The falling edge of this pin resets the W581XX IC completely just as if a power-on reset had been performed. The W581XX begins the POI process on the rising edge of this pin. The device may function abnormally and cause unpredictable operation if VDD is not discharged to ground and the W581XX is powered up again. This pin can be used to reset the W581XX. 10. SPK The SPK pin is a current type voice output connected to the internal D/A converter. The full-scale output of the 8-bit D/A converter is 5mA. This output is sufficient to drive an external 8 ohm speaker by using an external low-power NPN transistor with a 120~160 beta value, such as an 8050D, or its equivalent. - 6- W581xx Design Guide FUNCTIONAL DESCRIPTION 1. Instruction Sets The W581XX family PowerSpeechTM program instruction sets include unconditional and conditional instructions. Most of these instructions are programmed by writing "LD (Load)" and "JP (Jump)" commands and by modifying the contents of the R0~R7, EN, STOP, and MODE registers. Registers A. R0~R7 Register Rn (n:0~7) is an 8-bit register that stores the entry values from 0 to 255 voice groups. The structure of this register is shown below: Rn: Bit: 7 6 5 4 3 2 1 0 The default value of Rn is 0. B. EN Register EN is an 8-bit register that stores the rising/falling edge enable or disable status information for all trigger pins. This information determines whether each trigger pin is retriggerable, non-retriggerable, overwrite, or non-overwrite. The 8-bit structure of this register and the rising or falling edge of the triggers corresponding to each bit are shown below: EN: Bit: 7 Trigger: 4r 3r 2r 1r 4f 3f 2f 1f 6 5 4 3 2 1 0 The digits 1 to 4 represent TG1 to TG4, respectively; "r" represents the rising edge; and "f" represents the falling edge. When any one of the eight bits is set to "1," the rising or falling edge of the corresponding trigger pin can be enabled, interrupting the current state. The default value of EN register is "1111 1111"". C. STOP Register The STOP register stores stop output status information to determine the voltage level of each stop output pin. The 8-bit structure of this register and the stop output pin corresponding to each bit are shown below: - 7- W581xx Design Guide STOP: Bit: 7 STOP: X 6 X 5 X 4 STPE 3 STPD 2 STPC 1 STPB 0 STPA "X" indicates a "don't care" bit. The default value of the STOP register is "1111 1111" D. MODE Register The MODE register is used to store operand information to select the various operating modes as shown below. MODE: Bit: 7 MODE: Flash/DC LED2/STPC X Long/Short debounce time X X X X 6 5 4 3 2 1 0 A "1" for one of these bits selects the first of the pair of modes indicated; a "0" selects the second of the pair. Bit 7 is used to determine the output status of LED1 and/or LED2: Flash alternate or synchronous output (by mask option), or DC (LED will be lit constantly without flashing). Bit 6 determines whether pin15 acts as a LED output pin or STOP output pin. Bit 4 is used to determine whether the debounce time for all trigger inputs is Long (around 45 mS) or Short ( around 350S) time. The default value of the MODE register is "11X1 XXXX", that is "Flash, LED2, X, Long debounce time, X,X,X,X" Commands A. Unconditional Instructions Load (LD) command: This command can load value or operand data into the Rn (n:0~7), EN, STOP, or MODE register. LD Rn, value: This instruction is used to load a voice group entry value into register Rn (n:0~7), as shown in the following example. Example: - 8- W581xx Design Guide LD R0, 167 (decimal) 0xA7 (hexadecimal) 1 LD EN, operand: 0 1 0 0 1 1 1 B Value: 0 to 255 This instruction is used to define the trigger interrupt settings by loading the operand message into register EN. The following example illustrates how the settings are defined. Example: LD EN, 0x41 (hexadecimal) 0100 0001 (binary) 0 TG: Group: 4r 7 1 3r 6 0 2r 5 0 1r 4 0 4f 3 0 3f 2 0 2f 1 1 1f 0 a. When the rising edge of TG3 (3r) is activated, the EN register will cause TG3 to interrupt the current playing state and jump immediately to voice group 6, the voice group that corresponds to 3r. b. When the falling edge of TG1 goes active, the EN register will cause TG1 to interrupt the current playing state and jump immediately to voice group 0, the voice group that corresponds to 1f. c. No action will be taken when the other trigger pins are pressed, because the corresponding bits are set to "0." LD STOP, operand: This instruction loads the operand message into the STOP register to set the output levels of the stop signals. When a particular STOP bit is set to "0," the corresponding stop signal will be an active low output. Example: LD STOP, 0x53 0 STOP: X 1 X 0 X 1 STPE 0 0 1 STPB 1 STPA STPD STPC a. The STPA, STPB and STPE output signals will be high outputs. b. The STPC and STPD output signals will be low outputs. c. The bit6 "1" is a "don't care" bit and so has no effect on the stop signal output setting. - 9- W581xx Design Guide LD MODE, operand: This instruction is used to select among various operating modes. It loads an operand message into the MODE register to select one mode from each of several pairs of modes. A "1" for one of these bits selects the first of the pair of modes indicated; a "0" selects the second of the pair. The following example describes the MODE setting of the W581XX product. Example: LD MODE, 0xD0 1 1 0 1 0 0 0 0 MODE: Flash LED2 don't care Long time don't care a. The LED is set as a flash type, with the flash frequency 3 Hz. b. Pin 15 (LED2/STPC) is configured as the LED2 output pin. c. The bit5 is a "do not care" bit because the 4th pin of W581XX is fixed as TG4 pin. d. The debounce time of the trigger inputs is set to long time (around 45 mS) JUMP (JP) Command: JP value: Instructs the device to jump directly to the voice group corresponding to the value indicated. The voice group value may range from 0 to 127. JP Rn (n:0~7): Instructs the device to jump to whatever voice group is indicated by the value currently stored in register Rn. B. Conditional Instructions: Conditional instructions are executed only when the conditions specified in the instructions hold. The conditional instructions are listed below. An explanation of the notation used in the instructions follows. (Note: There are no conditional instructions for LD MODE.) Load (LD) command: LD Rn (n:0~7), value @LAST: Load the voice group entry value into Rn when the last global repeat sound cycle is finished. - 10 - W581xx Design Guide LD Rn (n:0~7), value @TGm_HIGH (or_LOW): If the m-th (m: 1 to 4) trigger pin status is kept at "High" (or "Low") voltage level, then load the value into Rn register. LD EN, operand @LAST: Load the operand message into the EN register when the last global repeat sound cycle is finished. LD STOP, operand @LAST: Load the operand message into the STOP register when the last global repeat sound cycle is finished. Jump (JP) command: JP value @LAST: When the last global repeat sound cycle is finished, jump to the group entry value indicated (range: 0 to 127) and begin execution. JP Rn (n:0~7) @LAST: When the last global repeat sound cycle is finished, jump to the group entry value indicated by the Rn register and begin execution. JP value @TGm_HIGH (or _LOW): _ If the m-th (m: 1 to 4) trigger pin is kept at "High" (or "Low") voltage level, then jump to the indicated value (range: 0 to 127) and begin execution. JP Rn (n:0~7) @TGm_HIGH (or _LOW): _ If the m-th (m: 1 to 4) trigger pin is kept at "High" (or "Low") voltage level, then jump to the group entry value indicated by the Rn register and begin execution. C. End Instruction: END: This command instructs the chip to immediately cease all activity. - 11 - W581xx Design Guide D. Instruction Set List: INSTRUCTION RANGE DESCRIPTION DEFAULT VALUE LD Rn, value (n:0~7) Unconditional LD EN, operand LD STOP, operand LD MODE, operand JP value JP Rn (n:0~7) Conditional LD Rn, value @LAST (n:0~7) LD Rn, value @TGm_HIGH (n:0~7) LD Rn, value @TGm_LOW (n:0~7) LD EN, operand @LAST LD STOP, operand @LAST JP value @LAST 0-255 - - - 0-127 0-255 0-255 0-255 0-255 - - 0-127 Rn o value EN o operand STOP o operand MODE o operand Jump to the group entry value indicated Jump to the group entry indicated by Rn If last global repeat finished, Rn o value If TGm (m:1- 4 ) status is high level, Rn o value If TGn (m:1-4 ) status is low level, Rn o value If last global repeat finished, EN o operand If last global repeat finished, STOP o operand If last global repeat finished, jump to the group entry value indicated If last global repeat finished, jump to the group entry value indicated in Rn If TGm (m: 1- 4) status is high level, jump to the group entry value indicated If TGm (m: 1- 4) status is low level, jump to the group entry value indicated If TGm (m: 1- 4) status is high level, jump to the group entry value indicated in Rn. If TGm (m: 1- 4) status is low level, jump to the group entry value indicated in Rn Stop all activity and enter standby state 0000 0000 1111 1111 xxx1 1111 11x1 xxxx - - - - - - - - JP Rn @LAST (n:0~7) 0-255 - JP value @TGm_HIGH 0-127 - JP value @TGm_LOW 0-127 - JP Rn @TGm_HIGH (n:0~7) 0-255 - JP Rn @TGm_LOW (n:0~7) 0-255 - END END - - 12 - W581xx Design Guide 2. Mask Option Description The mask options of the W581XX Enhanced PowerSpeechTM are used to select features that cannot be programmed through the chip's registers. The W581XX provides seven mask options, which are listed in the following table: MASK OPTION LED flash type (Asynchronous/Synchronous) LED volume controlled (No/Yes) LED1: section-controlled (Yes/No) LED2: section-controlled /STPC-controlled The 16th pin defined INSTRUCTION LED_ASYN; (default) LED_SYN LED_VOL_OFF; (default) LED_VOL_ON LED1_S_CTL; (default) LED1_S_OFF LED2_S_CTL; (default) LED2_STC_CTL STPD ; (default) FTEST The 17th pin defined STPE; (default) BUSY Normal/CPU mode setting NORMAL; (default) CPU Notes: 1.The demo chip for the W581XX series is the W58100. 2. Mask options can be configured automatically by the W58100. DEMO CHIP OPTION - If LED_VOL_ON is set, the other mask options will be redundant - - For W58100 only STPD is provided If in CPU mode, the default item is BUSY. - 3. Speech Equation Description Speech equations are used to define the combination of playback sounds. The following is an example of a speech equation format: i:N H4+m1*(A_flv+m2*(B_flv+m3*(C_flv+m4*D_flv)))+...T4 m4*[1FFFF] END where - 13 - W581xx Design Guide (1). i defines the group number (from 0 to 255). (2). N defines the number of global repeats (from 1 to 16). (3). m1, m2, m3 and m4 define the number of local repeats (from 1 to 7). (4). A, B, C, and D are files containing ADPCM converted voice data. (5). _flv is the section control setting, for which the parameters f, l and v are as follows: f: Sampling Frequency define (default value: f=2) f Frequency 3 8 KHz 2 6 KHz 1 4.8 KHz 0 4 KHz I: LED status define (default value: l=0) l LED status 1 On 0 Off v: Fading Effect define (default value: v=7) The max. value of the voice is v=7, that is the full scale of the sound. The min. value is v=0, that is 0.1 times of the full scale of the sound. The volume value from large to small is 7> 6> 5> 4> 3> 2> 1> 0. Note 1: If the section control setting is not defined, the default values are used. For example, in the speech equation H4+A+T4, if the A sound is played, the default values are used. These values are: 6K Hz sampling frequency (f=2), LED off (l=0), and maximum volume output (v=7). Note 2: If the section control setting is defined, both the f and l digits must be defined together. The v digit is optional. For example: 1. H4+A_2+T4: This is a wrong speech equation since only one digit (f) of section control is defined. 2. H4+A_21+T4: This is a correct speech equation with section control. The sampling frequency is 6K Hz (f=2), the LED is ON (l=1), and the volume is maximum value (v=7, the default value). 3. H4+A_210+T4: This is a complete speech equation with section control. The sampling frequency is 6K Hz (f=2), the LED is ON (l=1), and the volume is minimum value (v=0). (6). [1FFFF] is a period of silence of length 1FFFF (around 5.46 seconds) under the 6K Hz sampling frequency condition. The maximum silence length in one "[ ]" is [FFFFF], that is 1M bits, around 43.69 seconds under the 6K Hz sampling frequency condition. The silence can't be placed between voices and H4/T4 that will generate a little noise. It is necessary to place it on one line as above example that will gain a good silence. - 14 - W581xx Design Guide (7). H4 and T4 are the Head file and Tail file with 4-bit ADPCM data format. These two files can be used to eliminate the popping sound which may occur when the sound starts and stops. The following is a sample waveform: V 1/2V H4 0.25Kbit T4 0.25Kbit H4 0.25Kbit T4 0.25Kbit 0 [silence] If the voice (H4+....+T4) doesn't play smoothly, then NH4 and NT4 can be used to displace H4 and T4. By using NH4 and NT4 smooth playing voices can be created, however more ROM memory is required (around 0.66Kbits). (8). Flexible combination of unlimited "( )": This feature can be used in writing speech equations. This feature reduces program writing time but does not save program memory. For example: EQ1: H4+2*(A+2*(B+2*(C+3*D)))+T4 EQ2: H4+A+B+C+3*D+C+3*D+B+C+3*D+C+3*D+A+B+C+3*D+C+3*D+B+C+3*D+C+3*D+T4 These two speech equation are the same. After compiling, these two speech equations will occupy the same program memory size. Note that EQ1 is much easier to write and understand than EQ2. There is no limit in the number of "( )". However, each pair of "( )"" must be written on the same line. 4. Programmable Power-on Initialization Whenever the W581XX Enhanced PowerSpeechTM is powered on, the programs contained in the 32nd voice group will be executed immediately. Programs can therefore be written into this group to set the initial power-on state. If the user does not wish to execute any programs at power-on, an "END" instruction should be entered in group 32. 5. PowerSpeechTM Program Format TM The W581XX PowerSpeechTM has a programming language to define the product functions. An example of the W581XX PowerSpeechTM program format is shown below. Explanatory notes follow the example (for reference only) - 15 - W581xx Design Guide (6) ; (default)/ [LED_SYN ] ; (default)/ [LED1_S_OFF ] ; (default)/ [LED2_STC_CTL ] ; (default)/ [LED_VOL_ON ] ; (default)/ [FTEST ] ; (default)/ [BUSY ] ; (default)/ [CPU ] ; (default)/ [LED1 ] ; (default)/ [FREQ0, FREQ1, FREQ3 ] ; (default)/ [VOL0~VOL6] (1) W58105 LED_ASYN LED1_S_CTL LED2_S_CTL LED_VOL_OFF STPD STPE NORMAL LED0 FREQ2 VOL7 (2) (3) 32: (4) 0: (5) 2: 5 (7) H4+SN_013+SN_20+SN_316+T4 END 3 H4+S11+S2+T4 [1FF] END LD R0, 64 LD EN, 0X00 LD MODE, 0X90 LD STOP, 04 END (9) (8) ; disable all triggers ; LED flash, Stop C, 20 mS ; Stop C = 1, ; Stop A, Stop B, Stop D, Stop E = 0 Notes: (1) Bodies: The user must first define the enhanced PowerSpeechTM body to be used, or else an error message will appear during compiation. The enhanced PowerSpeechTM bodies include the following: W581XX: W58101, W58102, W58103, W58104, W58105, W58106, W58110, W58115, and W58120 (2) Mask Options: See above description. (3) Declarations: State the output frequency, LED on/off state and volume variable, as follows: LED on/off: -- LED0: LED off (default) -- LED1: LED on Output frequency: -- FREQ0: 4KHz -- FREQ1: 4.8 KHz -- FREQ2: 6 KHz (default) - 16 - W581xx Design Guide -- FREQ3: 8 KHz Volume Variable: -- VOL0: (minimum) 0.1 times volume of the full scale of the sound -- VOL1 -- VOL2 -- VOL3 -- VOL4 -- VOL5 -- VOL6 -- VOL7: (maximum) The full scale of the sound (default) (4) Program body: Write application program and speech operations, including the following: Define entry point of speech group. Determine the number of global repeats. Describe speech equations. Define the register values and instructions. Note 1: The maximum program memory size that can be used by the W581XX is 64K bits. Note 2: Every GO instruction occupies 48 bits, and every group entry value (0~255) occupies 16 bits. Therefore, a total of around 1,300 GO instructions can be used in a program. Note 3: The GO instruction includes the following contents: (a). Instruction set: Like "LD R0, XX", "JP R3 @TG2_LOW" ...etc. (b). END instruction: END (c). Every ADPCM file for the speech equations. For example, in the speech equation: H4+A+B_217+C+T4, there are a total of 5 GO instructions: H4, A, B_217, C, and T4. These GO instructions do not include the Mask Option and Declaration instructions. For example: (for reference only) W58105 LED_SYN LED1_S_CTL FREQ3 VOL5 32: ; Body define, 0 GO instruction ; Mask Option, 0 GO instruction ; Mask Option, 0 GO instruction ; Declaration, 0 GO instruction ; Declaration, 0 GO instruction ; POI group entry, 16 bits LD EN, 0X0F ; 48 bits, 1 GO instruction LD STOP, 0X10 ; 1 GO instruction END ; END instruction, 1 GO instruction ; Group entry, 16 bits. 0:3 - 17 - W581xx Design Guide ; The global repeat 3 occupied 4 bit ROM size included in the Group entry. LD EN, 0X00 ; 1 GO instruction LD STOP, 0X1F ; 1 GO instruction H4+3*A+B_217+C+T4 ; Speech equation, total with 6 GO [1FFF] ; instructions. Include: ; H4, 3*A, B_217, C, [1FFF], and T4. LD STOP, 0X10 ; 1 GO instruction LD EN, 0X0F ; 1 GO instruction END ; 1 GO instruction 1: H4+A+B+C_30+D+E+T4 [1FFF] END 2: JP 100 @TG4_LOW END 100: H4+3*(A+2*B)+T4 END ; 16 bits ; 8 GO instructions: ; H4, A, B, C_30, [1FFF], D, E, and T4 ; 1 GO instruction ; 16 bits ; 1 GO instruction ; 1 GO instruction ; 16 bits ; Equal to: H4+A+2*B+A+2*B+A+2*B+T4, total with 8 GO ; instructions. ; 1 GO instruction In the program example shown above, there are a total of 34 GO instructions and 101 group entries (= 100+1, because the maximum group entry to be used is 100). The total program memory size for this program is 3,248 bits (34*48+101*16=3248). Note 4: To use the 64K bits program memory size more efficiently, the following suggestions can be followed: (a). The voice groups should be used consecutively and without skipping. For example: 0, 1, 2, 3....255, is better than 0, 1, 100, 150... 255. (b). If the program includes several voice groups, then the voice group with the most GO instructions should be placed at the end of the program. (5) Group body: Define the voice group entry point. Product W581XX Group entry points 0-255 TG H/W entry points 0-7 Power-on entry point 32 (6) Note: A semicolon (";") is used to distinguish characters that are not part of the program. Characters written to the right of the semicolon are not considered part of the program. (7) Global Repeat: The global repeat instruction is "n" where n is from 1 to 16. This instruction must be placed on the same line as the group entry point. - 18 - W581xx Design Guide (8) Speech equation: These are used to define the combination of playback sounds. (9) Blank: A voice group entry point must be followed by one full blank line without any instructions or speech equations. 7. CPU interface The W581XX can communicate with an external microprocessor through a simple serial CPU interface. The voice group transmitted from CPU must between 128 and 255. It is shown below: Ts TH TG1 (data) TG2 (clock) BUSY Tclr Td Tdeb Tcrd TPl TPh Tclr > Tdeb, Tdeb = 256/Fs or 2/Fs depend on long or short debounce, which Fs is the speech sampling rate of last synthesized speech. Fs default value is 6kHz when power on or after reset. Tcrd > 5uS Ts > 500nS Th> 50nS Tpl > 500ns Tph > 500 ns Tzero < 128/Fs or 1/Fs depend on long or short debounce Td < 50 ns TG1 (data) TG2 (clock) Tclr Tzero Tdeb Tcrd Note: - 19 - W581xx Design Guide 1. Tdeb means the "Debounce time" which can be "Long" or "Short", depending on bit4 of the MODE register. If the MODE register has a "1" in bit4, then the debounce time will be set to "Long" If bit4 is "0"," then the debounce time will be set to "Short". In case of last synthesized speech sampling rate is 6kHz, for long debounce Tdeb = 256/6k = 42.7ms, for short debounce Tdeb = 2/6k = 333us. 2. Only when Tclr is longer than Tdeb, the receiving data counter of W581xx can be clear to zero. Considering about the speech sampling frequency may shift due to the deviation of component or voltage, at least 20% mark up,i.e. 42.7ms * (1 + 20%) = 51.2 ms for long debounce when the last synthesized speech sampling rate is 6kHz, is suggested to guarantee the success of debounce. For short debounce at 6kHz speech sampling rate, 333us * (1 + 20%) = 400 us were recommended. 3. Tcrd is the "CPU Reset Delay" time. 4. During data transfer phase, Tzero, the consecutive low state on TG1(data), could not be longer than half of debounce time Tdeb, otherwise it may be treated as a debounce and then reset the receiving data counter. For the same reason of possible frequency shift just like Tclr, 20% margin were suggested. At Fs = 6kHz and long debounce, the consecutive low state on TG1(Tzero) can not more than 0.5 * Tdeb * (1 - 20%) = 0.5 * 42.7 ms * 0.8 = 17 ms for long debounce and 0.5 * 333us * (1-20%) = 133 us for short debounce. To program W581XX in CPU mode, the CPU keyword must be added and TG1F/ TG1R/ TG2F/ TG2R must be disabled including the directly interrupt and condition commands. So In the CPU mode the "@TG1_high/low" and "@TG2_high/low" are illegal and bit0, bit1, bit4 and bit5 of the EN register must be set to "0". The following example shows this: (for reference only) W58105 CPU ; Reserved word, for CPU mode mask option LED1_S_CTL LED2_STC_CTL 32: LD EN,0X0C LD MODE,0X8F END 0: 1: 4: 5: END 162: H4+voice1+T4 END The waveform must be sent from the external C through TG1 and TG2 to control the playing of the voice group. The waveform looks like this: In the program example (for reference only) shown above, the C will transfer the number 162 to interrupt W581XX. The number 162 (decimal) is equal to 10100010b (binary). ; CPU interrupt ; disable TG1F/TG1R/TG2F/TG2R ; bit4 of the MODE register is 0 ; so the debounce time is selected "Short" (arround 350 S) - 20 - W581xx Design Guide LSB MSB 0 TG1 (data) TG2 (clock) <1> <2> <3> 1 0 0 0 1 0 1 <4> Tdeb Tcrd <1> When TG1 is pulled low, the W581XX stops playing voice or instructions and waits for data from the external C. <2> When TG1F debounces OK, the W581XX clears the CPU receiving buffer. <3> 8-bit data are transferred by TG1 (data) and TG2 (clock). The first bit of the data to be sent is the LSB . <4> TG1 returns high and starts the CPU interrupt. In this case W58105 will play the H4+voice1+T4 sections and the BUSY pin is pulled high until the "END" instruction is reached. Example: <1> Micro controller program (used W74C250 as the controller) ; W581 CPU mode test program ; W581 chosen the long debounce time ; W74C260 with the RC oscillator: 11 Kohm Rosc ; CLOCK pin connect to RE0 ; DATA pin connect to RE1 ; BUSY pin connect to RC3 addr_h equ ram20 ; store the W581CPU data, high byte addr_l equ ram21 ; low byte ;................................................ org 000h mov IEF,#00000000b ; disable all interrupt mov HEF,#00000000b mov PEF,#0000B jmp begin org 004h ; divider0 rtn org 008h ; timer0 rtn org 00ch jmp portrc org 014h ; divider1 rtn org 020h ; timer1 - 21 - W581xx Design Guide rtn ;................................................ begin: mov PM0,#1100B ; RC.3 as W581 busy pin mov PM1,#1111b ; RA is input pins mov PM2,#1111b ; RB is input pins mov wre,#1111b ; data and clock pins pulled high mov RE,wre mov RA,wre mov RB,wre ;........................................................ mov ram10,#2H ; power on waiting 200ms in order to DDD5b: mov ram11,#0FH ; complete W581 setup procedure DDD4b: mov ram12,#0FH DDD3b: mov ram13,#0FH DDD2b: mov ram14,#0FH DDD1b: dec ram14 jnz DDD1b dec ram13 jnz DDD2b dec ram12 jnz DDD3b dec ram11 jnz DDD4b dec ram10 jnz DDD5b ;........................................................ mov addr_h,#0010b ; send group 32 for POI mov addr_l,#0000b call playsound ;serial output subroutine mov IEF,#00000100b ; enable interrupt port RC mov HEF,#00000100b mov PEF,#1000B set128: mov addr_h,#1000b mov addr_l,#0000b sleep: en int Hold inc addr_l ; increment W581 address data mov wrf,addr_h ; from 128 to 255 adcr wrf,#0 mov addr_h,wrf jz set128 jmp sleep ;................................................ portrc: mova wre,rc xrl wre,#1111b jb3 W581CPU - 22 - W581xx Design Guide over_rc: clr rtn W581CPU: call playsound jmp over_rc ;................................................ playsound: mov wr8,#3 send_again: mov wr0,#1 mov RE,wr0 mov ram10,#08H DDD4a: mov ram11,#0FH DDD3a: mov ram12,#0FH DDD2a: mov ram13,#0FH DDD1a: dec ram13 jnz DDD1a dec ram12 jnz DDD2a dec ram11 jnz DDD3a dec ram10 jnz DDD4a mov wr0,#3 mov RE,wr0 nop nop nop nop ;................................................ mov acc,addr_l jb0 bit0_h mov wr0,#0 mov RE,wr0 mov wr0,#1 nop mov RE,wr0 jmp bit1 bit0_h: mov wr0,#2 mov RE,wr0 mov wr0,#3 nop mov RE,wr0 bit1: mov acc,addr_l jb1 bit1_h mov wr0,#0 mov RE,wr0 ; W581 play sound PSR0 ; retransmit 3 times ; make tg1 low ; tg1 low for >70mS to fit the long debounce time spec. ; Tcrd -> CPU reset time > 5S ; LSB first send ; bit0 <-- low ; bit0 <-- high ; bit 1 <-- low - 23 - W581xx Design Guide mov nop mov jmp bit1_h: mov mov mov nop mov bit2: mov jb2 mov mov mov nop mov jmp bit2_h: mov mov mov nop mov bit3: mov jb3 mov mov mov nop mov jmp bit3_h: mov mov mov nop mov bit4: mov jb0 mov mov mov nop mov jmp bit4_h: acc,addr_h bit4_h wr0,#0 RE,wr0 wr0,#1 RE,wr0 bit5 ; bit 4 <-- high wr0,#2 RE,wr0 wr0,#3 RE,wr0 acc,addr_l bit3_h wr0,#0 RE,wr0 wr0,#1 RE,wr0 bit4 ; bit 3 <-- high wr0,#2 RE,wr0 wr0,#3 RE,wr0 acc,addr_l bit2_h wr0,#0 RE,wr0 wr0,#1 RE,wr0 bit3 ; bit 2 <-- high wr0,#2 RE,wr0 wr0,#3 RE,wr0 wr0,#1 RE,wr0 bit2 ; bit 1 <-- high ; bit 2 <-- low ; bit 3 <-- low ; bit 4 <-- low - 24 - W581xx Design Guide mov mov mov nop mov bit5: mov jb1 mov mov mov nop mov jmp bit5_h: mov mov mov nop mov bit6: mov jb2 mov mov mov nop mov jmp bit6_h: mov mov mov nop mov bit7: mov jb3 mov mov mov nop mov jmp bit7_h: mov mov mov nop mov wr0,#2 RE,wr0 wr0,#3 RE,wr0 acc,addr_h bit7_h wr0,#0 RE,wr0 wr0,#1 RE,wr0 oversend ; bit 7 <-- high wr0,#2 RE,wr0 wr0,#3 RE,wr0 acc,addr_h bit6_h wr0,#0 RE,wr0 wr0,#1 RE,wr0 bit7 ; bit 6 <-- high wr0,#2 RE,wr0 wr0,#3 RE,wr0 acc,addr_h bit5_h wr0,#0 RE,wr0 wr0,#1 RE,wr0 bit6 ; bit 5 <-- high wr0,#2 RE,wr0 wr0,#3 RE,wr0 ; for next nibble addr_h ; bit 5 <-- low ; bit 6 <-- low ; bit 7 <-- low - 25 - W581xx Design Guide oversend: mov mov mov mov dec jnz dec jnz mova skb3 jmp rtn wr0,#3 RE,wr0 ram12,#0FH ; delay >200uS ram13,#0FH ram13 D1a ram12 D2a wre,rc ; check BUSY pin high or not wre next_time ; if BUSY pin still low send the data again D2a: D1a: next_time: dskz wr8 jmp send_again rtn ;................................................ end VDD RE1 TG1 (DATA) AUD TG2 (CLOCK) RE0 W74C250 W581XX RC3 BUSY LED1 STB <2> W581xx CPU mode program w58104 CPU POI: ld mode,0xff ld en,0x00 END 128: h4+1+2+8+t4 END 129: h4+1+2+9+t4 END 130: h4+1+3+0+t4 END 131: h4+1+3+1+t4 END 132: h4+1+3+2+t4 END 133: h4+1+3+3+t4 - 26 - W581xx Design Guide END 134: h4+1+3+4+t4 END 135: h4+1+3+5+t4 END 136: h4+1+3+6+t4 END 137: h4+1+3+7+t4 END 138: h4+1+3+8+t4 END 139: h4+1+3+9+t4 END 140: h4+1+4+0+t4 END 141: h4+1+4+1+t4 END 142: h4+1+4+2+t4 END 143: h4+1+4+3+t4 END 144: h4+1+4+4+t4 END 145: h4+1+4+5+t4 END 146: h4+1+4+6+t4 END 147: h4+1+4+7+t4 END 148: h4+1+4+8+t4 END 149: h4+1+4+9+t4 END 150: h4+1+5+0+t4 END 151: h4+1+5+1+t4 END 152: h4+1+5+2+t4 END 153: h4+1+5+3+t4 END 154: h4+1+5+4+t4 END 155: h4+1+5+5+t4 END 156: h4+1+5+6+t4 END 157: h4+1+5+7+t4 END 158: h4+1+5+8+t4 END 159: h4+1+5+9+t4 END 160: h4+1+6+0+t4 END 161: h4+1+6+1+t4 END 162: h4+1+6+2+t4 END 163: h4+1+6+3+t4 END 164: h4+1+6+4+t4 END 165: h4+1+6+5+t4 END 166: h4+1+6+6+t4 END - 27 - W581xx Design Guide 167: h4+1+6+7+t4 END 168: h4+1+6+8+t4 END 169: h4+1+6+9+t4 END 170: h4+1+7+0+t4 END 171: h4+1+7+1+t4 END 172: h4+1+7+2+t4 END 173: h4+1+7+3+t4 END 174: h4+1+7+4+t4 END 175: h4+1+7+5+t4 END 176: h4+1+7+6+t4 END 177: h4+1+7+7+t4 END 178: h4+1+7+8+t4 END 179: h4+1+7+9+t4 END 180: h4+1+8+0+t4 END 181: h4+1+8+1+t4 END 182: h4+1+8+2+t4 END 183: h4+1+8+3+t4 END 184: h4+1+8+4+t4 END 185: h4+1+8+5+t4 END 186: h4+1+8+6+t4 END 187: h4+1+8+7+t4 END 188: h4+1+8+8+t4 END 189: h4+1+8+9+t4 END 190: h4+1+9+0+t4 END 191: h4+1+9+1+t4 END 192: h4+1+9+2+t4 END 193: h4+1+9+3+t4 END 194: h4+1+9+4+t4 END 195: h4+1+9+5+t4 END 196: h4+1+9+6+t4 END 197: h4+1+9+7+t4 END 198: h4+1+9+8+t4 END 199: h4+1+9+9+t4 END 200: - 28 - W581xx Design Guide h4+2+0+0+t4 END 201: h4+2+0+1+t4 END 202: h4+2+0+2+t4 END 203: h4+2+0+3+t4 END 204: h4+2+0+4+t4 END 205: h4+2+0+5+t4 END 206: h4+2+0+6+t4 END 207: h4+2+0+7+t4 END 208: h4+2+0+8+t4 END 209: h4+2+0+9+t4 END 210: h4+2+1+0+t4 END 211: h4+2+1+1+t4 END 212: h4+2+1+2+t4 END 213: h4+2+1+3+t4 END 214: h4+2+1+4+t4 END 215: h4+2+1+5+t4 END 216: h4+2+1+6+t4 END 217: h4+2+1+7+t4 END 218: h4+2+1+8+t4 END 219: h4+2+1+9+t4 END 220: h4+2+2+0+t4 END 221: h4+2+2+1+t4 END 222: h4+2+2+2+t4 END 223: h4+2+2+3+t4 END 224: h4+2+2+4+t4 END 225: h4+2+2+5+t4 END 226: h4+2+2+6+t4 END 227: h4+2+2+7+t4 END 228: h4+2+2+8+t4 END 229: h4+2+2+9+t4 END 230: h4+2+3+0+t4 END 231: h4+2+3+1+t4 END 232: h4+2+3+2+t4 END 233: h4+2+3+3+t4 - 29 - W581xx Design Guide END 234: h4+2+3+4+t4 END 235: h4+2+3+5+t4 END 236: h4+2+3+6+t4 END 237: h4+2+3+7+t4 END 238: h4+2+3+8+t4 END 239: h4+2+3+9+t4 END 240: h4+2+4+0+t4 END 241: h4+2+4+1+t4 END 242: h4+2+4+2+t4 END 243: h4+2+4+3+t4 END 244: h4+2+4+4+t4 END 245: h4+2+4+5+t4 END 246: h4+2+4+6+t4 END 247: h4+2+4+7+t4 END 248: h4+2+4+8+t4 END 249: h4+2+4+9+t4 END 250: h4+2+5+0+t4 END 251: h4+2+5+1+t4 END 252: h4+2+5+2+t4 END 253: h4+2+5+3+t4 END 254: h4+2+5+4+t4 END 255: h4+2+5+5+t4 END 8. Programming Examples (for reference only) This section presents several programming examples for the W581XX enhanced PowerSpeechTM chips. User programs should be written in ASCII code using a text editor. After compiling, the sound effects resulting from the programs can be tested by using a Winbond demo board. Example1: Four playing mode settings: a. One-shot Trigger Mode 0: LD EN, 0X01 H4+sound+T4 ; TG1 falling edge group entry point ; Enable TG1 falling edge input only - 30 - W581xx Design Guide END The timing diagram for this example is shown below: CASE 1: TG1: AUD: Sound 1 CASE 2: TG1: AUD: Sound 1 b. Level Hold Trigger Mode 0: LD EN, 0X11 H4+sound1+T4 JP 0 4: END The timing diagram is shown below: ; TG1 rising edge group entry point ; TG1 falling edge group entry point ; Enable TG1 falling and rising edge input CASE 1: TG1: Stop immediately CASE 2: TG1: Stop immediately AUD: AUD: S1 S1 c. Completed Cycle Level Hold 0: LD EN, 0X01 H4+sound1+T4 JP 0 @TG1_LOW END The timing diagram is shown below: ; If TG1 state is low, jump to 0 entry point ; TG1 falling edge group entry point ; Enable TG1 falling edge input only - 31 - W581xx Design Guide CASE 1: TG1: AUD: S1 CASE 2: TG1: S1 S1 AUD: d. Single Cycle Level Hold 0: LD EN, 0X11 H4+sound1+T4 END 4: END The timing diagram is shown below: CASE 1: TG1: Stop immediately ; TG1 falling edge group entry point ; Enable TG1 falling and rising edge input CASE 2: TG1: AUD: S1 AUD: Example 2: Retriggerable and Non-retriggerable setting a. Retriggerable: 0: LD EN, 0x01 . . . END The timing diagram is shown below: TG1: AUD: Restart Restart Sound 1 Sound 1 b. Non-retriggerable: - 32 - W581xx Design Guide 0: LD EN, 0x00 . . . LD EN, 0x11 END The timing diagram is shown below: TG1: AUD: Sound 1 Sound 1 Example 3: Serial Playing Mode (5 segments) W58105 32: LD R0, 8 LD EN, 0X01 END 0: JP R0 8: LD R0, 9 H4+S1+T4 END 9: LD R0, 10 H4+S2+T4 END 10: LD R0, 11 H4+S3+T4 END 11: LD R0, 12 H4+S4+T4 END 12: LD R0, 8 H4+S5+T4 END The timing diagram is shown below: TG1 1 2 3 5 1 AUD S1 S2 S3 S5 S1 - 33 - W581xx Design Guide Example 4: Random (1) W58105 32: LD EN, 0X01 LD R0, 8 END 0: LD EN, 0X00 JP R0 8: JP 18 @TG1_HIGH 9: JP 19 @TG1_HIGH 10: JP 20 @TG1_HIGH 11: JP 21 @TG1_HIGH JP 8 31: LD EN, 0X01 END 21: H4+S4+T4 LD R0, 10 20: H4+S3+T4 LD R0, 11 JP 31 19: H4+S2+T4 LD R0, 8 JP 31 18: H4+S1+T4 LD R0, 9 JP 31 The timing diagram is shown below: TG1 1 2 3 5 1 ... ... AUD S3 S1 S4 S4 S2 Example 5: Random (2) W58105 32: LD EN, 0X11 END 0: LD R0, 8 [300] LD R0, 9 [300] 10: H4+S5+T4 9: H4+S1+T4 END 8: H4+S4+T4 END - 34 - W581xx Design Guide LD R0, 10 [300] LD R0, 11 [300] LD R0, 12 [300] JP 0 4: JP R0 12: 11: END H4+S3+T4 END H4+S2+T4 END The timing diagram is shown below: TG1 1 2 3 5 1 ... ... AUD S5 S1 S3 S2 S4 7. Application Examples (for reference only) The following paragraph presents several special application examples. Example 1: Power-on Trigger: If one of the trigger pins is grounded, then the sound corresponding to that trigger will be played out at power-on. Program: W58105 32: LD EN, 0X00 JP 8 @TG1_LOW JP 9 @TG2_LOW JP 10 @TG3_LOW JP 11 @TG4_LOW LD EN, 0X0F 0: 8: H4+S1+T4 LD EN, 0X0F END 1: 3: 11: H4+S4+T4 LD EN, 0X0F END 2: 10 H4+S3+END LD EN, 0X0F END 9: H4+S2+T4 LD EN, 0X0F END - 35 - W581xx Design Guide Application Circuit: VDD VDD TG1 TG2 TG3 TG4 AUD W581XX LED1 STB STA Example 2: 8 TG Input Application: In this application, the 4 trigger inputs are expanded to 8 trigger inputs. Program: W58105 32: LD MODE, 0XA0 LD STOP, 0X00 LD EN, 0X0F END 0: LD STOP, 0X01 JP 8 @TG1_HIGH H4+V1+T4 LD STOP, 0X00 END 8: H4+V2+T4 LD STOP, 0X00 END 1: LD STOP, 0X01 JP 9 @TG2_HIGH H4+V3+T4 LD STOP, 0X00 END 9: ; STPA set to high level ; check high ; play V3 ; STPA set to low level ; pseudo trigger pin ; STPA set to high level ; check high ; play V1 ; STPA set to low level ; pseudo trigger pin ; play V2 ; STPA set to low level ; STPA set to low level ; One Shot play mode - 36 - W581xx Design Guide ; play V4 ; STPA set to low level H4+V4+T4 LD STOP, 0X00 END 2: LD STOP, 0X01 JP 10 @TG3_HIGH H4+V5+T4 LD STOP, 0X00 END 10: H4+V6+T4 LD STOP, 0X00 END 3: LD STOP, 0X01 JP 11 @TG4_HIGH H4+V7+T4 LD STOP, 0X00 END 11: H4+V8+T4 LD STOP, 0X00 END ; STPA set to high level ; check high ; play V5 ; STPA set to low level ; pseudo trigger pin ; play V6 ; STPA set to low level ; STPA set to high level ; check high ; play V7 ; STPA set to low level ; pseudo trigger pin ; play V8 ; STPA set to low level Application Circuit VDD V1 V2 V3 V4 V5 V6 V7 V8 TG4 LED1 STB STA TG3 AUD TG2 TG1 W581XX Delay time: V1~V8: 2mS + debounce time - 37 - W581xx Design Guide Example 3: Fading Effect Application This program will play the "voice" with a reducing volume. The STOP signals will be turned off (1: on, 0: off) one by one. Program: W58105 32: LD MODE, 0X10 LD STOP, 0X00 LD EN, 0X0F END 0: LD STOP,0X1F H4+voice_217 LD STOP,0X1E voice_306 voice_215 LD STOP,0X1C voice_304 voice_213 LD STOP,0X18 voice_302 LD STOP,0X10 voice_211 LD STOP,0X00 voice_300+T4 END ; STPA, B, C, D, E turn ON ; sample rate= 6K, LED1 turn ON, volume= 7 (the biggest) ; STPB, C, D, E turn ON, STPA turn OFF ; sample rate= 8K, LED1 turn OFF, volume= 6 ; sample rate= 6K, LED1 turn ON, volume= 5 ; STPC, D, E turn ON, STPA, B turn OFF ; sample rate= 8K, LED1 turn OFF, volume= 4 ; sample rate= 6K, LED1 turn ON, volume= 3 ; STPD, E turn ON, STPA, B, C turn OFF ; sample rate= 8K, LED1 turn OFF, volume= 2 ; STPE turn ON, STPA, B, C, D turn OFF ; sample rate= 6K, LED1 turn ON, volume= 1 ; STPA, B, C, D, E turn OFF ; sample rate= 8K, LED1 turn OFF, volume= 0 ; pin15 set as STPC output ; set STPA, STPB, and STPC = 0 Example 4: Register Application This program combines one sentence when TG1 is triggered before. It will then play a sentence with the TG2 voice and TG3 voice. TG2 and TG3 are sequence functions. Words for TG2 and TG3 can be chosen and trigger TG1 will play the combined sentence. Program: W58105 32: LD EN,0x00 LD MODE, 0X10 LD STOP, 0xff LD R1,10 LD R2,20 LD R3,10 ; pin15 set as STPC output ; set STPA, STPB, STPC, STPD, STPE = 1 ; set R1, R2, R3, R4 initial data - 38 - W581xx Design Guide LD R4,20 LD EN, 0X07 END 0: LD STOP,0xfe JP R3 1: JP R1 2: JP R2 10: LD R1, 11 LD R3, 10 H4+I+am+T4 JP R4 @TG4_LOW END 11: LD R1, 12 LD R3, 11 H4+you+are+T4 JP R4 @TG4_LOW END 12: LD R1, 10 LD R3, 12 H4+she+is+T4 JP R4 @TG4_LOW END 20: LD R2, 21 LD R4, 20 LD STOP, 0xff H4+a+pretty+woman+T4 END 21: LD R2, 22 LD R4, 21 LD STOP, 0xff H4+an+ugly+girl+T4 END 22: LD R2, 20 ; enable TG1, TG2, TG3 ; TG1 plays the combined sentence ; set TG4 low as the combine function flag ; play the R3+R4 voice ; play sequentially Voice1 --> Voice2 --> Voice3 --> Voice1... ; play sequentially Voice4 --> Voice5 --> Voice6 --> Voice4... ; Voice1 ; Voice2 ; Voice3 ; set STPA, STPB, STPC, STPD, STPE = 1 ; Voice4 ; set STPA, STPB, STPC, STPD, STPE = 1 ; Voice5 - 39 - W581xx Design Guide LD R4, 22 LD STOP, 0xff H4+a+fat+lady+T4 END ; set STPA, STPB, STPC, STPD, STPE = 1 ; Voice6 Application Circuit VDD TG1 AUD TG2 W581XX TG3 TG4 LED1 STB STA - 40 - W581xx Design Guide Revision History Version E Date April 22nd, 1999 Writer Sophia Ho Reasons for change * Modify CPU mode and add an example of 4bit control program - 41 - |
Price & Availability of W518XXDESIGNGUIDE
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |